1. Field of the Invention
The present invention relates to a clock signal generator such as a PLL (Phase Locked Loop) circuit for outputting a synchronizing clock signal synchronized with input data comprising a digital signal, and to a data signal generator including the clock signal generator, for generating a digital signal based on input data and synchronizing with a clock signal.
2. Description of the Prior Art
A clock signal generator for outputting a synchronizing clock signal synchronized with input data has been disclosed in Japanese Patent Application Laid-Open No. 6-326599.
Japanese Patent Application Laid-Open No. 6-326599 shows a random walk filter having a phase comparator and a variable dividing ratio counter as the prior art example. The phase comparator of the random walk filter compares the phase of the edge of the input data and the phase of a reproduced clock pulse (synchronizing clock signal). The phase comparator outputs a lead signal when the reproduced clock pulse leads the input data, an equiphase signal when the reproduced clock pulse is equal to the input data, an d a lag signal when the reproduced clock pulse lags behind the input data.
Further, the variable dividing ratio counter divides the frequency of the clock pulse by a dividing ratio K when the counter has received the equiphase signal from the phase comparator to output a reproduced clock pulse. The variable dividing ratio counter divides the frequency of the clock pulse by a dividing ratio K+1 to output a reproduced clock pulse when receiving the lead signal from the phase comparator. The variable dividing ratio counter divides the frequency of the clock pulse by a dividing ratio K-1 to output a reproduced clock pulse when receiving the lag signal from the phase comparator.
Japanese Patent Application Laid-Open No. 6-326599 also discloses a clock signal generator in which even if the speed of received data varies, a shift-reduced clock can be reproduced. The clock signal generator is a clock pulse reproduction circuit having a phase comparator, a variable dividing ratio counter, a first counter, a second counter, a comparing means and a dividing ratio changing means. The first counter of the clock pulse reproduction circuit counts the number of times that the phase comparator outputs a lead signal within a predetermined period. The second counter counts the number of times that the phase comparator outputs a lag signal within the predetermined period. The comparing means compares the count value of the first counter and that of the second counter. The dividing ratio changing means varies the dividing ratio of the variable dividing ratio counter in accordance with the result of the comparison by the comparing means.
Recently, a transmitted FM-multiplexed signal has been obtained by superimposing a digital signal comprising character information on an FM sound signal. Receivers receiving the FM-multiplexed signal can recover the character information as well as enjoy the FM sound, displaying the character information on a character information display panel.
The digital signal superimposed on the FM sound signal, which is made up of the character information, is transferred at a predetermined transfer rate, normally, 16 kHz. However, the influence of noise and a change in the receiving state deteriorate the signal in S/N ratio and in phase stability. Because of the superimposition of noise, the digital signal input to the receiving side varies in phase, producing error data and the loss of data. Thus, the transfer rate of the digital signal is not necessarily set to the predetermined transfer rate in every data.
When the clock signal generator described as the first prior art captures the digital signal having a poor S/N ratio as the input data and produces the synchronizing clock signal (reproduced clock pulse) based on the input data, the following problems have arisen.
Where the phase of the input data is unstable, the dividing ratio output from the dividing ratio counter takes any of K, K-1 and K+1. As a result, the phase of the synchronizing clock signal often changes, producing an unstable state. At worst, the unstable state makes it difficult to synchronize the input data with the synchronizing clock signal.
Meanwhile, the clock signal generator described as the second prior art is considered to be effective for producing a regular phase shift to some extent, as in the case where the input data is fast or slow in speed. However, the generator has difficulty in synchronizing the input data with the synchronizing clock signal when a digital signal having a low S/N ratio is captured as the input data.